Overview

The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.

  • 2 - 0.7 V HCSL differential output pairs
  • Phase jitter: PCIe Gen2 < 3.1 ps rms
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 33-110 MHz operation in PLL mode
  • 10-110 MHz operation in Bypass mode

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    Buy / Sample
    Part Number
    9DB102BGILF
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    Samples Available
    		 TSSOP 20 I Yes Tube 1 2.951 Get Samples,
    9DB102BGILFT
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    		TSSOP 20 I Yes Reel 1 2.489
    9DB102BGLF
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    Samples Available
    		 TSSOP 20 C Yes Tube 1 2.515 Get Samples,
    9DB102BGLFT
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    		TSSOP 20 C Yes Reel 1 2.121
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