Overview

The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB233 suitable for Express Card applications.

  • 2- 0.7 V HCSL differential output pairs
  • Phase jitter: PCIe Gen3 < 1 ps rms
  • Phase jitter: PCIe Gen2 < 3.1 ps rms
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 33-110 MHz operation in PLL mode
  • 10-110 MHz operation in Bypass mode

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    Buy / Sample
    Part Number
    9DB233AGILF
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    Samples Available
    		 TSSOP 20 I Yes Tube 1 Get Samples,
    9DB233AGILFT
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    		TSSOP 20 I Yes Reel 1 2.658
    9DB233AGLF
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    Samples Available
    		 TSSOP 20 C Yes Tube 1 2.95 Get Samples,
    9DB233AGLFT
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    		TSSOP 20 C Yes Reel 1 2.488
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