RZA Flexible Software Package Documentation  Release v1.1.0

 
Ethernet PHY (r_gether_phy)

Functions

fsp_err_t R_GETHER_PHY_Open (ether_phy_ctrl_t *const p_ctrl, ether_phy_cfg_t const *const p_cfg)
 Resets Ethernet PHY device. Implements ether_phy_api_t::open. More...
 
fsp_err_t R_GETHER_PHY_Close (ether_phy_ctrl_t *const p_ctrl)
 Close Ethernet PHY device. Implements ether_phy_api_t::close. More...
 
fsp_err_t R_GETHER_PHY_StartAutoNegotiate (ether_phy_ctrl_t *const p_ctrl)
 Starts auto-negotiate. Implements ether_phy_api_t::startAutoNegotiate. More...
 
fsp_err_t R_GETHER_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t *const p_ctrl, uint32_t *const p_line_speed_duplex, uint32_t *const p_local_pause, uint32_t *const p_partner_pause)
 Reports the other side's physical capability. Implements ether_phy_api_t::linkPartnerAbilityGet. More...
 
fsp_err_t R_GETHER_PHY_LinkStatusGet (ether_phy_ctrl_t *const p_ctrl)
 Returns the status of the physical link. Implements ether_phy_api_t::linkStatusGet. More...
 

Detailed Description

The Ethernet PHY module (r_gether_phy) provides an API for standard Ethernet PHY communications applications that use the E-MAC peripheral. It implements the Ethernet PHY Interface.

Overview

The Ethernet PHY module is used to setup and manage an external Ethernet PHY device for use with the on-chip Ethernet Controller (E-MAC) peripheral. It performs auto-negotiation to determine the optimal connection parameters between link partners. Once initialized the connection between the external PHY and the onboard controller is automatically managed in hardware.

Features

The Ethernet PHY module supports the following features:

Configuration

Build Time Configurations for r_gether_phy

The following build time configurations are defined in fsp_cfg/r_gether_phy_cfg.h:

ConfigurationOptionsDefaultDescription
Parameter Checking
  • Default (BSP)
  • Enabled
  • Disabled
Default (BSP) If selected code for parameter checking is included in the build.
Select PHY
  • Default
  • Other
  • KSZ8091RNB
  • KSZ8041
  • DP83620
  • KSZ9131RNXI
KSZ9131RNXI Select PHY chip to use. Selecting 'Default' will automatically choose the correct option when using a Renesas development board.
Reference Clock
  • Default
  • Enabled
  • Disabled
Default Select whether to use the RMII reference clock. Selecting 'Default' will automatically choose the correct option when using a Renesas development board.

Configurations for Networking > Gigabit Ethernet (r_gether_phy)

This module can be added to the Stacks tab via New Stack > Networking > Gigabit Ethernet (r_gether_phy).

ConfigurationOptionsDefaultDescription
NameName must be a valid C symbolg_gether_phy0 Module name.
Channel
  • 0
  • 1
1 Select the Ethernet controller channel number.
PHY-LSI AddressSpecify a value between 0 and 31.0 Specify the address of the PHY-LSI used.
PHY-LSI Reset Completion TimeoutSpecify a value between 0x1 and 0xFFFFFFFF.0x00020000 Specify the number of times to read the PHY-LSI control register while waiting for reset completion. This value should be adjusted experimentally based on the PHY-LSI used.
Select MII type
  • MII
  • RMII
RMII Specify whether to use MII or RMII.
MII/RMII Register Access Wait-timeSpecify a value between 0x1 and 0x7FFFFFFF.8 Specify the bit timing for MII/RMII register accesses during PHY initialization. This value should be adjusted experimentally based on the PHY-LSI used.
Voltage
  • 3.3V
  • 2.5V
  • 1.8V
3.3V Specify voltage.
Flow Control
  • Disable
  • Enable
Disable Select whether to enable or disable flow control.

Usage Notes

Note
See the example below for details on how to initialize the Ethernet PHY module.

Accessing the MII and RGMII Registers

Use the PIR register to access the MII and RGMII registers in the PHY-LSI. Serial data in the MII and RGMII management frame format is transmitted and received through the ETx_MDC and ETx_MDIO pins controlled by software.

MII and RGMII management frame format

The below table lists the MII and RGMII management frame formats.

Access type MII and RGMII management frame
Item PRE ST OP PHYAD REGAD TA DATA IDLE
Number of bits 32 2 2 5 5 2 16 1
Read 1...1 01 10 00001 RRRRR Z0 DDDDDDDDDDDDDDDD Z
Write 1...1 01 01 00001 RRRRR 10 DDDDDDDDDDDDDDDD Z
Note
- PRE (preamble): Send 32 consecutive 1s.
- ST (start of frame): Send 01b.
- OP (operation code): Send 10b for read or 01b for write.
- PHYAD (PHY address): Up to 32 PHY-LSIs can be connected to one MAC. PHY-LSIs are selected with these 5 bits. When the PHY-LSI address is 1, send 00001b.
- REGAD (register address): One register is selected from up to 32 registers in the PHY-LSI. When the register address is 1, send 00001b.
- TA (turnaround): Use 2-bit turnaround time to avoid contention between the register address and data during a read operation.
Send 10b during a write operation. Release the bus for 1 bit during a read operation (Z is output).
(This is indicated as Z0 because 0 is output from the PHY-LSI on the next clock cycle.)
- DATA (data): 16-bit data. Sequentially send or receive starting from the MSB.
- IDLE (IDLE condition): Wait time before inputting the next MII or RGMII management format. Release the bus during a write
operation (Z is output). No control is required, because a bus was already released during a read operation.

Limitations

Examples

ETHER PHY Basic Example

This is a basic example of minimal use of the ETHER PHY in an application.

void ether_phy_basic_example (void)
{
fsp_err_t err = FSP_SUCCESS;
g_ether_phy0_ctrl.open = 0U;
g_ether_phy0_cfg.channel = 1;
uint32_t clock_freq_hz = 0U;
g_ioport.p_api->pinEthernetVoltageModeCfg(g_ioport.p_ctrl, ioprt_ch, IOPORT_ETHERNET_VOLTAGE_18);
g_ioport.p_api->pinEthernetModeCfg(g_ioport.p_ctrl, ioprt_ch, IOPORT_ETHERNET_MODE_RMII);
R_ETHER1->CCC_b.OPC = GETHER_OPC_MODE_RESET;
clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK);
R_BSP_SoftwareDelay(GETHER_ETHERC_INITIALIZATION_WAIT_CYCLE * BSP_DELAY_UNITS_SECONDS / clock_freq_hz + 1,
R_ETHER1->CCC_b.OPC = GETHER_OPC_MODE_CONFIG;
/* Initializes the module. */
err = R_GETHER_PHY_Open(&g_ether_phy0_ctrl, &g_ether_phy0_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Start auto negotiation. */
err = R_GETHER_PHY_StartAutoNegotiate(&g_ether_phy0_ctrl);
assert(FSP_SUCCESS == err);
/* Polling until link is established. */
while (FSP_SUCCESS != R_GETHER_PHY_LinkStatusGet(&g_ether_phy0_ctrl))
{
/* Do nothing */
}
/* Get link partner ability from phy interface. */
err = R_GETHER_PHY_LinkPartnerAbilityGet(&g_ether_phy0_ctrl,
&g_ether_phy0_line_speed_duplex,
&g_ether_phy0_local_pause,
&g_ether_phy0_partner_pause);
assert(FSP_SUCCESS == err);
/* Check current link status. */
err = R_GETHER_PHY_LinkStatusGet(&g_ether_phy0_ctrl);
assert(FSP_SUCCESS == err);
}

Data Structures

struct  ether_phy_instance_ctrl_t
 

Enumerations

enum  ether_phy_voltage_t
 

Data Structure Documentation

◆ ether_phy_instance_ctrl_t

struct ether_phy_instance_ctrl_t

ETHER PHY control block. DO NOT INITIALIZE. Initialization occurs when ether_phy_api_t::open is called.

Data Fields
uint32_t open Used to determine if the channel is configured.
ether_phy_cfg_t const * p_gether_phy_cfg Pointer to initial configurations.
volatile uint32_t * p_reg_cxr23 Pointer to E-MAC peripheral registers.
uint32_t local_advertise Capabilities bitmap for local advertising.

Enumeration Type Documentation

◆ ether_phy_voltage_t

Voltage

Enumerator
ETHER_PHY_VOLTAGE_33 

3.3V

ETHER_PHY_VOLTAGE_25 

2.5V

ETHER_PHY_VOLTAGE_18 

1.8V

Function Documentation

◆ R_GETHER_PHY_Open()

fsp_err_t R_GETHER_PHY_Open ( ether_phy_ctrl_t *const  p_ctrl,
ether_phy_cfg_t const *const  p_cfg 
)

Resets Ethernet PHY device. Implements ether_phy_api_t::open.

Return values
FSP_SUCCESSChannel opened successfully.
FSP_ERR_ASSERTIONPointer to GETHER_PHY control block or configuration structure is NULL.
FSP_ERR_ALREADY_OPENControl block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure.
FSP_ERR_INVALID_CHANNELInvalid channel number is given.
FSP_ERR_INVALID_POINTERPointer to p_cfg is NULL.
FSP_ERR_TIMEOUTPHY-LSI Reset wait timeout.

◆ R_GETHER_PHY_Close()

fsp_err_t R_GETHER_PHY_Close ( ether_phy_ctrl_t *const  p_ctrl)

Close Ethernet PHY device. Implements ether_phy_api_t::close.

Return values
FSP_SUCCESSChannel successfully closed.
FSP_ERR_ASSERTIONPointer to GETHER_PHY control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened

◆ R_GETHER_PHY_StartAutoNegotiate()

fsp_err_t R_GETHER_PHY_StartAutoNegotiate ( ether_phy_ctrl_t *const  p_ctrl)

Starts auto-negotiate. Implements ether_phy_api_t::startAutoNegotiate.

Return values
FSP_SUCCESSGETHER_PHY successfully starts auto-negotiate.
FSP_ERR_ASSERTIONPointer to GETHER_PHY control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened

◆ R_GETHER_PHY_LinkPartnerAbilityGet()

fsp_err_t R_GETHER_PHY_LinkPartnerAbilityGet ( ether_phy_ctrl_t *const  p_ctrl,
uint32_t *const  p_line_speed_duplex,
uint32_t *const  p_local_pause,
uint32_t *const  p_partner_pause 
)

Reports the other side's physical capability. Implements ether_phy_api_t::linkPartnerAbilityGet.

Return values
FSP_SUCCESSGETHER_PHY successfully get link partner ability.
FSP_ERR_ASSERTIONPointer to GETHER_PHY control block is NULL.
FSP_ERR_INVALID_POINTERPointer to arguments are NULL.
FSP_ERR_NOT_OPENThe control block has not been opened
FSP_ERR_ETHER_PHY_ERROR_LINKPHY-LSI is not link up.
FSP_ERR_ETHER_PHY_NOT_READYThe auto-negotiation isn't completed

◆ R_GETHER_PHY_LinkStatusGet()

fsp_err_t R_GETHER_PHY_LinkStatusGet ( ether_phy_ctrl_t *const  p_ctrl)

Returns the status of the physical link. Implements ether_phy_api_t::linkStatusGet.

Return values
FSP_SUCCESSGETHER_PHY successfully get link partner ability.
FSP_ERR_ASSERTIONPointer to GETHER_PHY control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened
FSP_ERR_ETHER_PHY_ERROR_LINKPHY-LSI is not link up.